1. Field of the Invention
The present invention relates to a semiconductor device, more particularly to an internal voltage generating circuit for a semiconductor device which receives or outputs data, such as a semiconductor memory device.
2. Description of Related Art
An internal voltage generating circuit of a typical semiconductor memory device includes an internal voltage generating circuit for a memory cell array and an internal voltage generating circuit for a peripheral circuit of the memory cell array such as a data IO (input/output) circuit and a data IO control circuit. An internal voltage generating circuit of double data rate (DDR) and RAMBUS semiconductor memory devices further include an internal voltage generating circuit for a delay locked loop (DLL).
The internal voltage generating circuit of the semiconductor memory device receives an external power voltage and compares a reference voltage for a memory cell array, a reference voltage for a peripheral circuit, and a reference voltage for a delay locked loop to an internal voltage for a memory cell array, an internal voltage for a peripheral circuit, and an internal voltage for a delay locked loop, respectively, to generate an internal voltage of a reference voltage level for a memory cell array, an internal voltage of a reference voltage level for a peripheral circuit, and an internal voltage of a reference voltage level for a delay locked loop.
FIG. 1 is a view illustrating a conventional internal voltage generating circuit. The internal voltage generating circuit includes a comparator 10 and a driver D. The driver D includes a PMOS transistor P.
The comparator 10 receives an external power voltage EVC as a power voltage and compares a reference voltage VREF to an internal voltage IVC to raise a level of a node A when the internal voltage IVC is higher than the reference voltage VREF or to lower a level of a node A when the internal voltage IVC is lower than the reference voltage VREF. The PMOS transistor P is improved in driving ability when a level of a node A is raised and is degraded in driving ability when a level of a node A is lowered, thereby maintaining the internal voltage IVC to the reference voltage VREF.
The internal voltage generating circuit for a memory cell array, the internal voltage generating circuit for a peripheral circuit and the internal voltage generating circuit for a delay locked loop have the same configuration as that of FIG. 1. The internal voltage is set to be lower in level than the external power voltage EVC.
As described above, the internal voltage generating circuit of the conventional semiconductor memory device generates a constant internal voltage independently from a data input/output bit number. However, as a data input/output bit number increases, a level drop of the internal voltage for the memory cell array does not occur, but level drops of the internal voltages for the peripheral circuit and/or the delay locked loop occur. Hence, there is a problem in that data access speed goes down.
In detail, the internal voltage for the memory cell array is applied to PMOS bit line sense amplifies to be used to amplify data of bit line pairs, but the number of the PMOS bit line sense amplifiers is not increased by an increase of a data input/output bit number during operation. Therefore, a voltage drop of the internal voltage for the memory cell array does not occur even though the data input/output bit number is increased. However, in the case of the internal voltage for the peripheral circuit and/or the delay locked loop, the number of circuit components is increased as a data input/output bit number is increased, whereby a voltage drop occurs leading to a slow data access speed.
Consequently, the internal voltage generating circuits for the peripheral circuit and/or the delay locked loop of the conventional semiconductor memory device are configured to generate a constant internal voltage regardless of a data input/output bit number, and thus when a data input/output bit number is increased a data access speed is degraded.
The above described problem of the conventional internal voltage generating circuit is explained focusing on the semiconductor memory device, but such a problem can occur in all semiconductor devices which receive or output data.